1. Field
This disclosure relates to electronic design automation (EDA). More specifically, this disclosure relates to techniques for tiered synchronization of schematics and layouts.
2. Related Art
Integrated circuit design often involves the use of schematics, which typically contain logical representations of components and wires in integrated circuits. EDA tools are typically used for creating schematics. For example, a schematic editor may allow a designer to create an electronic schematic of an integrated circuit. The electronic schematic may then be used by other EDA tools to simulate the operation of the integrated circuit, create a layout of the integrated circuit, and/or detect errors in the schematic.
In particular, EDA tools may use schematic-driven-layout (SDL) to automatically generate and place components in a layout based on a reference schematic for creating the layout. Once the layout is created, the EDA tools may perform a layout-versus-schematic (LVS) check to ensure that the layout matches the schematic. Any mismatches found in the LVS check may be presented to the designer so that the designer may modify the layout and/or schematic to repair the mismatches. For example, LVS checks may locate errors such as shorts, opens, component mismatches, missing components, and/or property errors in the layout. The designer may use the errors to modify the layout until the layout passes the LVS check.
However, conventional SDL and LVS mechanisms typically include a tradeoff between performance and speed. For example, an LVS check based on graph labeling and/or graph isomorphism may perform a thorough comparison of the layout and schematic but may also be computationally expensive. On the other hand, an efficient LVS check that requires components in the layout and schematic to be “label coherent” may be of limited use after modifications are made to the layout and/or schematic.
Hence, integrated circuit design may be improved through mechanisms that increase both the speed and accuracy of synchronization between schematics and layouts.